Tegra186: reset power state info during CPU_ON

This patch resets the power state info for CPUs when onlining,
as we set deepest power when offlining a core but that may not
be requested by non-secure sw which controls idle states. It
will re-init this info from non-secure software when the core
come online.

Original change by Prashant Gaikwad <[email protected]>

Change-Id: Id6c2fa2b821c7705aafbb561a62348c36fd3abd8
Signed-off-by: Varun Wadekar <[email protected]>

diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index 8911e8f617cbe2507c1c6f5ed3fe95be547a0431..b5189183149ed31fc55dcd97d700c7eecc83a857 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -246,6 +246,18 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
        cpu_context_t *ctx = cm_get_context(NON_SECURE);
        gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
 
+       /*
+        * Reset power state info for CPUs when onlining, we set deepest power
+        * when offlining a core but that may not be requested by non-secure
+        * sw which controls idle states. It will re-init this info from
+        * non-secure software when the core come online.
+        */
+       write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
+       write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
+       write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
+       mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC1,
+               0, 0);
+
        /*
         * Check if we are exiting from deep sleep and restore SE
         * context if we are.